Voltage Cut Off Circuit Using Time Delay

This is a design for protection voltage. This circuit is called as high and low voltage cut off. The circuit is using time delay for cut off the voltage. This is a low cost and reliable circuit for protecting such equipments from damages. This is the figure of the circuit.


Whenever the power line is switched on it gets connected to the appliance only after a delay of a fixed time. If there is hi/low fluctuations beyond sets limits the appliance get disconnected. The system tries to connect the power back after the specific time delay, the delay being counted from the time of disconnection. If the power down time (time for which the voltage is beyond limits) is less than the delay time, the power resumes after the delay: If it is equal or more, then the power resumes directly. This circuit is using op-amp 741 and 555 IC for control the operation.

The complete circuit is consisting of various stages. They are: - Dual rail power supply, Reference voltage source, Voltage comparators for hi/low cut offs, Time delay stage and Relay driver stage. Under normal operating conditions i.e. when the input voltage is between maximum and minimum limit the output from the both the comparators are low. The transistor Q1 is OFF and the relay is in de-energized (pole connected to N/C pin) state and the output is obtained. When the input voltage is below or above the limits set by the pre-sets R8 or R9, the output of the Op-Amps goes either low or high and diodes D1 or D2 would be forward biased depending on the situation. Transistor Q1 switches ON and the flow of current from collector to emitter energizes the relay and the output is cutoff.

SPI Interface Circuit for Big 7 Segment LED

This circuit is uses for the general purpose Big LED with SPI serial interfacing. The circuit is using a serial-in-parallel out shift register, 74HC595 for receiving serial data from microcontroller board. This is the figure of the circuit.


For wiring the schematic is SER is for data input, SRCLK is shift clock and RCLK is Latch clock. Each data bit is shifted into the register on rising edge of the shift clock. When all data bits are shifted into the 8-bit register, the rising edge of RCLK will clock the data to be latched at each output bit, i.e. QA - QH. The Big LED is made from cheap dot LED. Each segment has five dot LED connected in series with a limiting resistor tied to +12V. The logic high at the input of ULN2003 makes the output active low, thus sinks the LED current into the chip. The driver has 7-bit for segment a, b, c, d, e, f, and g. Q1 is for optional point display.

Multiple digits can easily be made by connecting the QH to the next digit serial input bit, see the circuit below. Please note that, the shift clock and latch signal are tied to every 74HC595.